/* Generated automatically by the program `genoutput' from the machine description file `md'. */ #include "config.h" #include "system.h" #include "flags.h" #include "ggc.h" #include "rtl.h" #include "tm_p.h" #include "function.h" #include "regs.h" #include "hard-reg-set.h" #include "real.h" #include "insn-config.h" #include "conditions.h" #include "insn-flags.h" #include "insn-attr.h" #include "insn-codes.h" #include "recog.h" #include "toplev.h" #include "output.h" static const char * const output_0[] = { "mov %0 = %1", "addl %0 = %1, r0", "ld1%O1 %0 = %1%P1", "st1%Q0 %0 = %1%P0", "getf.sig %0 = %1", "setf.sig %0 = %1", }; static const char * const output_1[] = { "mov %0 = %1", "addl %0 = %1, r0", "ld2%O1 %0 = %1%P1", "st2%Q0 %0 = %1%P0", "getf.sig %0 = %1", "setf.sig %0 = %1", }; static const char * const output_2[] = { "mov %0 = %1", "addl %0 = %1, r0", "movl %0 = %1", "ld4%O1 %0 = %1%P1", "st4%Q0 %0 = %1%P0", "getf.sig %0 = %1", "setf.sig %0 = %1", "mov %0 = %1", "getf.s %0 = %1", "setf.s %0 = %1", }; static const char * const output_3[] = { "mov %0 = %1", "addl %0 = %1, r0", "movl %0 = %1", "ld8%O1 %0 = %1%P1", "st8%Q0 %0 = %1%P0", "getf.sig %0 = %1", "setf.sig %0 = %1", "mov %0 = %1", "getf.d %0 = %1", "setf.d %0 = %1", "mov %0 = %1", "mov %0 = %1", }; static const char * const output_8[] = { "mov %0 = %F1", "ldfs %0 = %1%P1", "stfs %0 = %F1%P0", "getf.s %0 = %F1", "setf.s %0 = %1", "mov %0 = %1", "ld4%O1 %0 = %1", }; static const char * const output_9[] = { "mov %0 = %F1", "ldfd %0 = %1%P1", "stfd %0 = %F1%P0", "getf.d %0 = %F1", "setf.d %0 = %1", "mov %0 = %1", }; static const char * const output_10[] = { "mov %0 = %F1", "ldf %0 = %1%P1", "stf %0 = %F1%P0", }; static const char * const output_13[] = { "sxt4 %0 = %1", "fsxt.r %0 = %1, %1%B0", }; static const char * const output_14[] = { "zxt1 %0 = %1", "ld1%O1 %0 = %1%P1", }; static const char * const output_15[] = { "zxt2 %0 = %1", "ld2%O1 %0 = %1%P1", }; static const char * const output_16[] = { "zxt4 %0 = %1", "ld4%O1 %0 = %1%P1", "fsxt.r %0 = f1, %1%B0", }; static const char * const output_35[] = { "add %0 = %1, %2", "adds %0 = %2, %1", "addl %0 = %2, %1", }; static const char * const output_41[] = { "add %0 = %1, %2", "adds %0 = %2, %1", "addl %0 = %2, %1", }; static const char * const output_86[] = { "and %0 = %2, %1", "fand %0 = %2, %1%B0", }; static const char * const output_87[] = { "andcm %0 = %2, %1", "fandcm %0 = %2, %1%B0", }; static const char * const output_88[] = { "or %0 = %2, %1", "for %0 = %2, %1%B0", }; static const char * const output_89[] = { "xor %0 = %2, %1", "fxor %0 = %2, %1%B0", }; static const char * const output_99[] = { "#", "cmp4.ne %0, %I0 = %1, r0", "ld4%O1 %0 = %1%P1", "st4%Q0 %0 = %1%P0", }; static const char *output_100 PARAMS ((rtx *, rtx)); static const char * output_100 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { return ia64_expand_prediction (insn, "(%%J0) br.cond.%s %%l2"); } static const char *output_101 PARAMS ((rtx *, rtx)); static const char * output_101 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { return ia64_expand_prediction (insn, "(%%j0) br.cond.%s %%l2"); } static const char *output_108 PARAMS ((rtx *, rtx)); static const char * output_108 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[3] = current_insn_predicate; if (operands[3] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J3) br.call.%s.many %2 = %0"); else return "br.call.sptk.many %2 = %0"; } } static const char *output_109 PARAMS ((rtx *, rtx)); static const char * output_109 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[3] = current_insn_predicate; if (operands[3] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J3) br.call.%s.many %2 = %0"); else return "br.call.sptk.many %2 = %0"; } } static const char *output_110 PARAMS ((rtx *, rtx)); static const char * output_110 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[4] = current_insn_predicate; if (operands[4] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J4) br.call.%s.many %3 = %1"); else return "br.call.sptk.many %3 = %1"; } } static const char *output_111 PARAMS ((rtx *, rtx)); static const char * output_111 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[4] = current_insn_predicate; if (operands[4] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J4) br.call.%s.many %3 = %1"); else return "br.call.sptk.many %3 = %1"; } } static const char *output_112 PARAMS ((rtx *, rtx)); static const char * output_112 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[5] = current_insn_predicate; if (operands[5] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J5) br.call.%s.many %4 = %2"); else return "br.call.sptk.many %4 = %2"; } } static const char *output_115 PARAMS ((rtx *, rtx)); static const char * output_115 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { return ia64_expand_prediction (insn, "(%%J0) br.ret.%s.many rp"); } static const char *output_116 PARAMS ((rtx *, rtx)); static const char * output_116 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { return ia64_expand_prediction (insn, "(%%j0) br.ret.%s.many rp"); } static const char * const output_120[] = { "add %0 = %1, %2", "adds %0 = %2, %1", "addl %0 = %2, %1", }; static const char * const output_269[] = { "(%J2) mov %0 = %1", "(%J2) addl %0 = %1, r0", "(%J2) ld1%O1 %0 = %1%P1", "(%J2) st1%Q0 %0 = %1%P0", "(%J2) getf.sig %0 = %1", "(%J2) setf.sig %0 = %1", }; static const char * const output_270[] = { "(%J2) mov %0 = %1", "(%J2) addl %0 = %1, r0", "(%J2) ld2%O1 %0 = %1%P1", "(%J2) st2%Q0 %0 = %1%P0", "(%J2) getf.sig %0 = %1", "(%J2) setf.sig %0 = %1", }; static const char * const output_271[] = { "(%J2) mov %0 = %1", "(%J2) addl %0 = %1, r0", "(%J2) movl %0 = %1", "(%J2) ld4%O1 %0 = %1%P1", "(%J2) st4%Q0 %0 = %1%P0", "(%J2) getf.sig %0 = %1", "(%J2) setf.sig %0 = %1", "(%J2) mov %0 = %1", "(%J2) getf.s %0 = %1", "(%J2) setf.s %0 = %1", }; static const char * const output_272[] = { "(%J2) mov %0 = %1", "(%J2) addl %0 = %1, r0", "(%J2) movl %0 = %1", "(%J2) ld8%O1 %0 = %1%P1", "(%J2) st8%Q0 %0 = %1%P0", "(%J2) getf.sig %0 = %1", "(%J2) setf.sig %0 = %1", "(%J2) mov %0 = %1", "(%J2) getf.d %0 = %1", "(%J2) setf.d %0 = %1", "(%J2) mov %0 = %1", "(%J2) mov %0 = %1", }; static const char * const output_277[] = { "(%J2) mov %0 = %F1", "(%J2) ldfs %0 = %1%P1", "(%J2) stfs %0 = %F1%P0", "(%J2) getf.s %0 = %F1", "(%J2) setf.s %0 = %1", "(%J2) mov %0 = %1", "(%J2) ld4%O1 %0 = %1", }; static const char * const output_278[] = { "(%J2) mov %0 = %F1", "(%J2) ldfd %0 = %1%P1", "(%J2) stfd %0 = %F1%P0", "(%J2) getf.d %0 = %F1", "(%J2) setf.d %0 = %1", "(%J2) mov %0 = %1", }; static const char * const output_279[] = { "(%J2) mov %0 = %F1", "(%J2) ldf %0 = %1%P1", "(%J2) stf %0 = %F1%P0", }; static const char * const output_282[] = { "(%J2) sxt4 %0 = %1", "(%J2) fsxt.r %0 = %1, %1%B0", }; static const char * const output_283[] = { "(%J2) zxt1 %0 = %1", "(%J2) ld1%O1 %0 = %1%P1", }; static const char * const output_284[] = { "(%J2) zxt2 %0 = %1", "(%J2) ld2%O1 %0 = %1%P1", }; static const char * const output_285[] = { "(%J2) zxt4 %0 = %1", "(%J2) ld4%O1 %0 = %1%P1", "(%J2) fsxt.r %0 = f1, %1%B0", }; static const char * const output_304[] = { "(%J3) add %0 = %1, %2", "(%J3) adds %0 = %2, %1", "(%J3) addl %0 = %2, %1", }; static const char * const output_310[] = { "(%J3) add %0 = %1, %2", "(%J3) adds %0 = %2, %1", "(%J3) addl %0 = %2, %1", }; static const char * const output_355[] = { "(%J3) and %0 = %2, %1", "(%J3) fand %0 = %2, %1%B0", }; static const char * const output_356[] = { "(%J3) andcm %0 = %2, %1", "(%J3) fandcm %0 = %2, %1%B0", }; static const char * const output_357[] = { "(%J3) or %0 = %2, %1", "(%J3) for %0 = %2, %1%B0", }; static const char * const output_358[] = { "(%J3) xor %0 = %2, %1", "(%J3) fxor %0 = %2, %1%B0", }; static const char * const output_368[] = { "#", "(%J2) cmp4.ne %0, %I0 = %1, r0", "(%J2) ld4%O1 %0 = %1%P1", "(%J2) st4%Q0 %0 = %1%P0", }; static const char *output_375 PARAMS ((rtx *, rtx)); static const char * output_375 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[3] = current_insn_predicate; if (operands[3] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J3) br.call.%s.many %2 = %0"); else return "br.call.sptk.many %2 = %0"; } } static const char *output_376 PARAMS ((rtx *, rtx)); static const char * output_376 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[3] = current_insn_predicate; if (operands[3] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J3) br.call.%s.many %2 = %0"); else return "br.call.sptk.many %2 = %0"; } } static const char *output_377 PARAMS ((rtx *, rtx)); static const char * output_377 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[4] = current_insn_predicate; if (operands[4] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J4) br.call.%s.many %3 = %1"); else return "br.call.sptk.many %3 = %1"; } } static const char *output_378 PARAMS ((rtx *, rtx)); static const char * output_378 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[4] = current_insn_predicate; if (operands[4] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J4) br.call.%s.many %3 = %1"); else return "br.call.sptk.many %3 = %1"; } } static const char *output_379 PARAMS ((rtx *, rtx)); static const char * output_379 (operands, insn) rtx *operands ATTRIBUTE_UNUSED; rtx insn ATTRIBUTE_UNUSED; { { operands[5] = current_insn_predicate; if (operands[5] != NULL_RTX) return ia64_expand_prediction (insn, "(%%J5) br.call.%s.many %4 = %2"); else return "br.call.sptk.many %4 = %2"; } } static const char * const output_385[] = { "(%J4) add %0 = %1, %2", "(%J4) adds %0 = %2, %1", "(%J4) addl %0 = %2, %1", }; extern int nonimmediate_operand PARAMS ((rtx, enum machine_mode)); extern int move_operand PARAMS ((rtx, enum machine_mode)); extern int register_operand PARAMS ((rtx, enum machine_mode)); extern int function_operand PARAMS ((rtx, enum machine_mode)); extern int sdata_symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int general_operand PARAMS ((rtx, enum machine_mode)); extern int const_int_operand PARAMS ((rtx, enum machine_mode)); extern int nonmemory_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_22bit_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_8bit_operand PARAMS ((rtx, enum machine_mode)); extern int scratch_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_fp01_operand PARAMS ((rtx, enum machine_mode)); extern int shift_32bit_count_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_6bit_operand PARAMS ((rtx, enum machine_mode)); extern int shladd_operand PARAMS ((rtx, enum machine_mode)); extern int shift_count_operand PARAMS ((rtx, enum machine_mode)); extern int normal_comparison_operator PARAMS ((rtx, enum machine_mode)); extern int adjusted_comparison_operator PARAMS ((rtx, enum machine_mode)); extern int reg_or_8bit_adjusted_operand PARAMS ((rtx, enum machine_mode)); extern int comparison_operator PARAMS ((rtx, enum machine_mode)); extern int immediate_operand PARAMS ((rtx, enum machine_mode)); extern int predicate_operator PARAMS ((rtx, enum machine_mode)); extern int call_operand PARAMS ((rtx, enum machine_mode)); extern int call_multiple_values_operation PARAMS ((rtx, enum machine_mode)); extern int memory_operand PARAMS ((rtx, enum machine_mode)); extern int fetchadd_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_14bit_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_8bit_and_adjusted_operand PARAMS ((rtx, enum machine_mode)); static const struct insn_operand_data operand_data[] = { { 0, "", VOIDmode, 0, 0 }, { nonimmediate_operand, "=r,r,r,m,r,*e", QImode, 0, 1 }, { move_operand, "r,J,m,r,*e,r", QImode, 0, 1 }, { nonimmediate_operand, "=r,r,r,m,r,*e", HImode, 0, 1 }, { move_operand, "r,J,m,r,*e,r", HImode, 0, 1 }, { nonimmediate_operand, "=r,r,r,r,m,r,*e,*e,r,*f", SImode, 0, 1 }, { move_operand, "r,J,i,m,r,*e,r,*e,*f,r", SImode, 0, 1 }, { nonimmediate_operand, "=r,r,r,r,m,r,*e,*e,r,*f,r,*b", DImode, 0, 1 }, { move_operand, "r,J,i,m,r,*e,r,*e,*f,r,*b,r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { function_operand, "s", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { sdata_symbolic_operand, "s", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { symbolic_operand, "", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { symbolic_operand, "s", DImode, 0, 1 }, { nonimmediate_operand, "=f,f,m,*r,f,*r,*r", SFmode, 0, 1 }, { general_operand, "fG,m,fG,fG,*r,*r,m", SFmode, 0, 1 }, { nonimmediate_operand, "=f,f,m,*r,f,*r", DFmode, 0, 1 }, { general_operand, "fG,m,fG,fG,*r,*r", DFmode, 0, 1 }, { nonimmediate_operand, "=f,f,m", XFmode, 0, 1 }, { general_operand, "fG,m,fG", XFmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", QImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", HImode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "r,*e", SImode, 0, 1 }, { register_operand, "=r,r", DImode, 0, 1 }, { nonimmediate_operand, "r,m", QImode, 0, 1 }, { register_operand, "=r,r", DImode, 0, 1 }, { nonimmediate_operand, "r,m", HImode, 0, 1 }, { register_operand, "=r,r,*e", DImode, 0, 1 }, { nonimmediate_operand, "r,m,*e", SImode, 0, 1 }, { register_operand, "=f,f", DFmode, 0, 1 }, { register_operand, "0,f", SFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", XFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", XFmode, 0, 1 }, { register_operand, "=f", XFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { nonmemory_operand, "rP", DImode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { reg_or_0_operand, "rO", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=r,r,r", SImode, 0, 1 }, { register_operand, "%r,r,a", SImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", SImode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { reg_or_8bit_operand, "rK", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=e", SImode, 0, 1 }, { register_operand, "e", SImode, 0, 1 }, { nonmemory_operand, "e", SImode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { register_operand, "%r,r,a", DImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { reg_or_8bit_operand, "rK", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { scratch_operand, "=X", DImode, 0, 0 }, { register_operand, "=&r", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { nonmemory_operand, "rI", DImode, 0, 1 }, { scratch_operand, "=e", DImode, 0, 0 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "%f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "%f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "%f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { shift_32bit_count_operand, "n", SImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { shift_32bit_count_operand, "n", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_6bit_operand, "rM", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shladd_operand, "n", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=&r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shladd_operand, "n", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { nonmemory_operand, "rI", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shift_count_operand, "M", DImode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "%r,*e", DImode, 0, 1 }, { reg_or_8bit_operand, "rK,*e", DImode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "r,*e", DImode, 0, 1 }, { reg_or_8bit_operand, "rK,*e", DImode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { normal_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", SImode, 0, 1 }, { reg_or_8bit_operand, "rK", SImode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { adjusted_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", SImode, 0, 1 }, { reg_or_8bit_adjusted_operand, "rL", SImode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { normal_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_8bit_operand, "rK", DImode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { adjusted_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_8bit_adjusted_operand, "rL", DImode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { comparison_operator, "", CCmode, 0, 0 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { comparison_operator, "", CCmode, 0, 0 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { immediate_operand, "n", DImode, 0, 1 }, { nonimmediate_operand, "=r,c,r,m", CCmode, 0, 1 }, { move_operand, "c,r,m,r", CCmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,r,m,r,r,m,r", DImode, 0, 1 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,0,0,rI,m,r,rI", DImode, 0, 1 }, { reg_or_22bit_operand, "rI,m,r,0,0,0,rI", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "=r,r", DImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "rI,rI", DImode, 0, 1 }, { reg_or_22bit_operand, "0,rI", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "=r,r,m,r,r,m,r", SImode, 0, 1 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,0,0,rI,m,r,rI", SImode, 0, 1 }, { reg_or_22bit_operand, "rI,m,r,0,0,0,rI", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "=r,r", SImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,rI", SImode, 0, 1 }, { reg_or_22bit_operand, "rI,rI", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { register_operand, "=rf", VOIDmode, 0, 1 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { call_multiple_values_operation, "", VOIDmode, 0, 0 }, { register_operand, "=rf", VOIDmode, 0, 1 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { register_operand, "b", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { register_operand, "%r,r,a", DImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", DImode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { const_int_operand, "i", DImode, 0, 1 }, { const_int_operand, "i", DImode, 0, 1 }, { const_int_operand, "i", DImode, 0, 1 }, { const_int_operand, "i", DImode, 0, 1 }, { memory_operand, "=m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { memory_operand, "=m", XFmode, 0, 1 }, { register_operand, "f*e", XFmode, 0, 1 }, { register_operand, "=f*e", XFmode, 0, 1 }, { memory_operand, "m", XFmode, 0, 1 }, { memory_operand, "m", BLKmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { fetchadd_operand, "n", SImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { fetchadd_operand, "n", DImode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "+m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "+m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { general_operand, "", QImode, 0, 1 }, { general_operand, "", QImode, 0, 1 }, { general_operand, "", HImode, 0, 1 }, { general_operand, "", HImode, 0, 1 }, { general_operand, "", SImode, 0, 1 }, { general_operand, "", SImode, 0, 1 }, { general_operand, "", DImode, 0, 1 }, { general_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { function_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { symbolic_operand, "", DImode, 0, 1 }, { general_operand, "", SFmode, 0, 1 }, { general_operand, "", SFmode, 0, 1 }, { general_operand, "", DFmode, 0, 1 }, { general_operand, "", DFmode, 0, 1 }, { general_operand, "", XFmode, 0, 1 }, { general_operand, "", XFmode, 0, 1 }, { register_operand, "", DFmode, 0, 1 }, { register_operand, "", SFmode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { const_int_operand, "", DImode, 0, 1 }, { const_int_operand, "", DImode, 0, 1 }, { nonmemory_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { reg_or_22bit_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { reg_or_8bit_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { reg_or_14bit_operand, "", DImode, 0, 1 }, { scratch_operand, "", DImode, 0, 0 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { nonmemory_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { nonmemory_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { shladd_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { reg_or_14bit_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { nonmemory_operand, "", DImode, 0, 1 }, { register_operand, "", SImode, 0, 1 }, { reg_or_8bit_and_adjusted_operand, "", SImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { reg_or_8bit_and_adjusted_operand, "", DImode, 0, 1 }, { reg_or_fp01_operand, "", SFmode, 0, 1 }, { reg_or_fp01_operand, "", SFmode, 0, 1 }, { reg_or_fp01_operand, "", DFmode, 0, 1 }, { reg_or_fp01_operand, "", DFmode, 0, 1 }, { reg_or_fp01_operand, "", XFmode, 0, 1 }, { reg_or_fp01_operand, "", XFmode, 0, 1 }, { nonimmediate_operand, "", CCmode, 0, 1 }, { move_operand, "", CCmode, 0, 1 }, { register_operand, "", CCmode, 0, 1 }, { register_operand, "", CCmode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "", CCmode, 0, 1 }, { reg_or_22bit_operand, "", DImode, 0, 1 }, { reg_or_22bit_operand, "", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "", DImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "", DImode, 0, 1 }, { reg_or_22bit_operand, "", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "", CCmode, 0, 1 }, { reg_or_22bit_operand, "", SImode, 0, 1 }, { reg_or_22bit_operand, "", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { register_operand, "", SImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "", SImode, 0, 1 }, { reg_or_22bit_operand, "", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { 0, "", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { 0, "", VOIDmode, 0, 0 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { memory_operand, "", OImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { general_operand, "", VOIDmode, 0, 1 }, { general_operand, "", VOIDmode, 0, 1 }, { general_operand, "", VOIDmode, 0, 1 }, { general_operand, "", VOIDmode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "", DImode, 0, 1 }, { memory_operand, "", OImode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { nonmemory_operand, "", SImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { nonmemory_operand, "", DImode, 0, 1 }, { nonimmediate_operand, "=r,r,r,m,r,*e", QImode, 0, 1 }, { move_operand, "r,J,m,r,*e,r", QImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c", CCmode, 0, 1 }, { nonimmediate_operand, "=r,r,r,m,r,*e", HImode, 0, 1 }, { move_operand, "r,J,m,r,*e,r", HImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c", CCmode, 0, 1 }, { nonimmediate_operand, "=r,r,r,r,m,r,*e,*e,r,*f", SImode, 0, 1 }, { move_operand, "r,J,i,m,r,*e,r,*e,*f,r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c,c,c,c,c", CCmode, 0, 1 }, { nonimmediate_operand, "=r,r,r,r,m,r,*e,*e,r,*f,r,*b", DImode, 0, 1 }, { move_operand, "r,J,i,m,r,*e,r,*e,*f,r,*b,r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c,c,c,c,c,c,c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { function_operand, "s", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { sdata_symbolic_operand, "s", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { symbolic_operand, "", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { symbolic_operand, "s", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { nonimmediate_operand, "=f,f,m,*r,f,*r,*r", SFmode, 0, 1 }, { general_operand, "fG,m,fG,fG,*r,*r,m", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { nonimmediate_operand, "=f,f,m,*r,f,*r", DFmode, 0, 1 }, { general_operand, "fG,m,fG,fG,*r,*r", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c", CCmode, 0, 1 }, { nonimmediate_operand, "=f,f,m", XFmode, 0, 1 }, { general_operand, "fG,m,fG", XFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", QImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", HImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "r,*e", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=r,r", DImode, 0, 1 }, { nonimmediate_operand, "r,m", QImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=r,r", DImode, 0, 1 }, { nonimmediate_operand, "r,m", HImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=r,r,*e", DImode, 0, 1 }, { nonimmediate_operand, "r,m,*e", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c", CCmode, 0, 1 }, { register_operand, "=f,f", DFmode, 0, 1 }, { register_operand, "0,f", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", XFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", XFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", XFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { const_int_operand, "n", DImode, 0, 1 }, { nonmemory_operand, "rP", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { reg_or_0_operand, "rO", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,r,r", SImode, 0, 1 }, { register_operand, "%r,r,a", SImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { reg_or_8bit_operand, "rK", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=e", SImode, 0, 1 }, { register_operand, "e", SImode, 0, 1 }, { nonmemory_operand, "e", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { register_operand, "%r,r,a", DImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { reg_or_8bit_operand, "rK", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { scratch_operand, "=X", DImode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=&r", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { register_operand, "e", DImode, 0, 1 }, { nonmemory_operand, "rI", DImode, 0, 1 }, { scratch_operand, "=e", DImode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "%f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "%f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { register_operand, "f", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "%f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { register_operand, "f", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { shift_32bit_count_operand, "n", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { shift_32bit_count_operand, "n", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_6bit_operand, "rM", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shladd_operand, "n", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=&r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shladd_operand, "n", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { nonmemory_operand, "rI", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { shift_count_operand, "M", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "%r,*e", DImode, 0, 1 }, { reg_or_8bit_operand, "rK,*e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=r,*e", DImode, 0, 1 }, { register_operand, "r,*e", DImode, 0, 1 }, { reg_or_8bit_operand, "rK,*e", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { normal_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", SImode, 0, 1 }, { reg_or_8bit_operand, "rK", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { adjusted_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", SImode, 0, 1 }, { reg_or_8bit_adjusted_operand, "rL", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { normal_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_8bit_operand, "rK", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { adjusted_comparison_operator, "", CCmode, 0, 0 }, { register_operand, "r", DImode, 0, 1 }, { reg_or_8bit_adjusted_operand, "rL", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { comparison_operator, "", CCmode, 0, 0 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { reg_or_fp01_operand, "fG", SFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { comparison_operator, "", CCmode, 0, 0 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { reg_or_fp01_operand, "fG", DFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=c", CCmode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { immediate_operand, "n", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { nonimmediate_operand, "=r,c,r,m", CCmode, 0, 1 }, { move_operand, "c,r,m,r", CCmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "c", CCmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,r,m,r,r,m,r", DImode, 0, 1 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,0,0,rI,m,r,rI", DImode, 0, 1 }, { reg_or_22bit_operand, "rI,m,r,0,0,0,rI", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { register_operand, "=r,r", DImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "rI,rI", DImode, 0, 1 }, { reg_or_22bit_operand, "0,rI", DImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { register_operand, "=r,r,m,r,r,m,r", SImode, 0, 1 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,0,0,rI,m,r,rI", SImode, 0, 1 }, { reg_or_22bit_operand, "rI,m,r,0,0,0,rI", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c,c,c,c,c", CCmode, 0, 1 }, { register_operand, "=r,r", SImode, 0, 1 }, { register_operand, "c,c", CCmode, 0, 1 }, { reg_or_22bit_operand, "0,rI", SImode, 0, 1 }, { reg_or_22bit_operand, "rI,rI", SImode, 0, 1 }, { predicate_operator, "", CCmode, 0, 0 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c", CCmode, 0, 1 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=rf", VOIDmode, 0, 1 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { call_multiple_values_operation, "", VOIDmode, 0, 0 }, { register_operand, "=rf", VOIDmode, 0, 1 }, { call_operand, "bi", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { register_operand, "=b", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "b", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "b", DImode, 0, 1 }, { 0, "", VOIDmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { register_operand, "%r,r,a", DImode, 0, 1 }, { reg_or_22bit_operand, "r,I,J", DImode, 0, 1 }, { register_operand, "=r,r,r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c,c,c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { register_operand, "+r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { memory_operand, "=m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { memory_operand, "=m", XFmode, 0, 1 }, { register_operand, "f*e", XFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=f*e", XFmode, 0, 1 }, { memory_operand, "m", XFmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { memory_operand, "m", BLKmode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { fetchadd_operand, "n", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { fetchadd_operand, "n", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", SImode, 0, 1 }, { memory_operand, "+m", SImode, 0, 1 }, { register_operand, "r", SImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, { register_operand, "=r", DImode, 0, 1 }, { memory_operand, "+m", DImode, 0, 1 }, { register_operand, "r", DImode, 0, 1 }, { predicate_operator, "", VOIDmode, 0, 0 }, { register_operand, "c", CCmode, 0, 1 }, }; const struct insn_data insn_data[] = { { "*movqi_internal", (const PTR) output_0, 0, &operand_data[1], 2, 0, 6, 2 }, { "*movhi_internal", (const PTR) output_1, 0, &operand_data[3], 2, 0, 6, 2 }, { "*movsi_internal", (const PTR) output_2, 0, &operand_data[5], 2, 0, 10, 2 }, { "*movdi_internal", (const PTR) output_3, 0, &operand_data[7], 2, 0, 12, 2 }, { "*load_fptr_internal1", "addl %0 = @ltoff(@fptr(%1)), gp", 0, &operand_data[9], 2, 0, 1, 1 }, { "load_gprel", "addl %0 = @gprel(%1), gp", (insn_gen_fn) gen_load_gprel, &operand_data[11], 2, 0, 1, 1 }, { "gprel64_offset", "movl %0 = @gprel(%1)", (insn_gen_fn) gen_gprel64_offset, &operand_data[13], 2, 0, 1, 1 }, { "*load_symptr_internal1", "addl %0 = @ltoff(%1), gp", 0, &operand_data[15], 2, 0, 1, 1 }, { "*movsf_internal", (const PTR) output_8, 0, &operand_data[17], 2, 0, 7, 2 }, { "*movdf_internal", (const PTR) output_9, 0, &operand_data[19], 2, 0, 6, 2 }, { "*movxf_internal", (const PTR) output_10, 0, &operand_data[21], 2, 0, 3, 2 }, { "extendqidi2", "sxt1 %0 = %1", (insn_gen_fn) gen_extendqidi2, &operand_data[23], 2, 0, 1, 1 }, { "extendhidi2", "sxt2 %0 = %1", (insn_gen_fn) gen_extendhidi2, &operand_data[25], 2, 0, 1, 1 }, { "extendsidi2", (const PTR) output_13, (insn_gen_fn) gen_extendsidi2, &operand_data[27], 2, 0, 2, 2 }, { "zero_extendqidi2", (const PTR) output_14, (insn_gen_fn) gen_zero_extendqidi2, &operand_data[29], 2, 0, 2, 2 }, { "zero_extendhidi2", (const PTR) output_15, (insn_gen_fn) gen_zero_extendhidi2, &operand_data[31], 2, 0, 2, 2 }, { "zero_extendsidi2", (const PTR) output_16, (insn_gen_fn) gen_zero_extendsidi2, &operand_data[33], 2, 0, 3, 2 }, { "extendsfdf2", "mov %0 = %1", (insn_gen_fn) gen_extendsfdf2, &operand_data[35], 2, 0, 2, 1 }, { "truncdfsf2", "fnorm.s %0 = %1%B0", (insn_gen_fn) gen_truncdfsf2, &operand_data[37], 2, 0, 1, 1 }, { "truncxfsf2", "fnorm.s %0 = %1%B0", (insn_gen_fn) gen_truncxfsf2, &operand_data[39], 2, 0, 1, 1 }, { "truncxfdf2", "fnorm.d %0 = %1%B0", (insn_gen_fn) gen_truncxfdf2, &operand_data[41], 2, 0, 1, 1 }, { "floatdixf2", "fcvt.xf %0 = %1", (insn_gen_fn) gen_floatdixf2, &operand_data[43], 2, 0, 1, 1 }, { "fix_truncsfdi2", "fcvt.fx.trunc %0 = %1%B0", (insn_gen_fn) gen_fix_truncsfdi2, &operand_data[45], 2, 0, 1, 1 }, { "fix_truncdfdi2", "fcvt.fx.trunc %0 = %1%B0", (insn_gen_fn) gen_fix_truncdfdi2, &operand_data[47], 2, 0, 1, 1 }, { "floatunsdisf2", "fcvt.xuf.s %0 = %1%B0", (insn_gen_fn) gen_floatunsdisf2, &operand_data[49], 2, 0, 1, 1 }, { "floatunsdidf2", "fcvt.xuf.d %0 = %1%B0", (insn_gen_fn) gen_floatunsdidf2, &operand_data[51], 2, 0, 1, 1 }, { "fixuns_truncsfdi2", "fcvt.fxu.trunc %0 = %1%B0", (insn_gen_fn) gen_fixuns_truncsfdi2, &operand_data[45], 2, 0, 1, 1 }, { "fixuns_truncdfdi2", "fcvt.fxu.trunc %0 = %1%B0", (insn_gen_fn) gen_fixuns_truncdfdi2, &operand_data[47], 2, 0, 1, 1 }, { "extv", "extr %0 = %1, %3, %2", (insn_gen_fn) gen_extv, &operand_data[53], 4, 0, 1, 1 }, { "extzv", "extr.u %0 = %1, %3, %2", (insn_gen_fn) gen_extzv, &operand_data[53], 4, 0, 1, 1 }, { "*insv_internal", "dep %0 = %3, %0, %2, %1", 0, &operand_data[57], 4, 0, 1, 1 }, { "shift_mix4left", "#", (insn_gen_fn) gen_shift_mix4left, &operand_data[61], 3, 0, 1, 1 }, { "*mix4left", "mix4.l %0 = %0, %r1", 0, &operand_data[61], 2, 0, 1, 1 }, { "mix4right", "mix4.r %0 = %r1, %0", (insn_gen_fn) gen_mix4right, &operand_data[64], 2, 0, 1, 1 }, { "*mix4right_3op", "mix4.r %0 = %2, %1", 0, &operand_data[66], 3, 0, 1, 1 }, { "*addsi3_internal", (const PTR) output_35, 0, &operand_data[69], 3, 0, 3, 2 }, { "*addsi3_plus1", "add %0 = %1, %2, 1", 0, &operand_data[72], 3, 0, 1, 1 }, { "*subsi3_internal", "sub %0 = %1, %2", 0, &operand_data[75], 3, 0, 1, 1 }, { "*subsi3_minus1", "sub %0 = %2, %1, 1", 0, &operand_data[72], 3, 0, 1, 1 }, { "*mulsi3_internal", "xma.l %0 = %1, %2, f0%B0", 0, &operand_data[78], 3, 0, 1, 1 }, { "*negsi2_internal", "sub %0 = r0, %1", 0, &operand_data[72], 2, 0, 1, 1 }, { "adddi3", (const PTR) output_41, (insn_gen_fn) gen_adddi3, &operand_data[81], 3, 0, 3, 2 }, { "*adddi3_plus1", "add %0 = %1, %2, 1", 0, &operand_data[84], 3, 0, 1, 1 }, { "subdi3", "sub %0 = %1, %2", (insn_gen_fn) gen_subdi3, &operand_data[87], 3, 0, 1, 1 }, { "*subdi3_minus1", "sub %0 = %2, %1, 1", 0, &operand_data[84], 3, 0, 1, 1 }, { "muldi3", "xma.l %0 = %1, %2, f0%B0", (insn_gen_fn) gen_muldi3, &operand_data[90], 3, 0, 1, 1 }, { "*madddi3", "xma.l %0 = %1, %2, %3%B0", 0, &operand_data[90], 5, 0, 1, 1 }, { "*madddi3_elim", "#", 0, &operand_data[95], 6, 0, 1, 1 }, { "smuldi3_highpart", "xma.h %0 = %1, %2, f0%B0", (insn_gen_fn) gen_smuldi3_highpart, &operand_data[90], 3, 0, 1, 1 }, { "umuldi3_highpart", "xma.hu %0 = %1, %2, f0%B0", (insn_gen_fn) gen_umuldi3_highpart, &operand_data[90], 3, 0, 1, 1 }, { "negdi2", "sub %0 = r0, %1", (insn_gen_fn) gen_negdi2, &operand_data[53], 2, 0, 1, 1 }, { "*popcnt", "popcnt %0 = %1", 0, &operand_data[53], 2, 0, 1, 1 }, { "addsf3", "fadd.s %0 = %1, %F2%B0", (insn_gen_fn) gen_addsf3, &operand_data[101], 3, 0, 1, 1 }, { "subsf3", "fsub.s %0 = %F1, %F2%B0", (insn_gen_fn) gen_subsf3, &operand_data[104], 3, 0, 1, 1 }, { "mulsf3", "fmpy.s %0 = %1, %2%B0", (insn_gen_fn) gen_mulsf3, &operand_data[107], 3, 0, 1, 1 }, { "abssf2", "fabs %0 = %1%B0", (insn_gen_fn) gen_abssf2, &operand_data[110], 2, 0, 1, 1 }, { "negsf2", "fneg %0 = %1%B0", (insn_gen_fn) gen_negsf2, &operand_data[110], 2, 0, 1, 1 }, { "*nabssf2", "fnegabs %0 = %1%B0", 0, &operand_data[110], 2, 0, 1, 1 }, { "minsf3", "fmin %0 = %1, %F2%B0", (insn_gen_fn) gen_minsf3, &operand_data[110], 3, 0, 1, 1 }, { "maxsf3", "fmax %0 = %1, %F2%B0", (insn_gen_fn) gen_maxsf3, &operand_data[110], 3, 0, 1, 1 }, { "*maddsf3", "fma.s %0 = %1, %2, %F3%B0", 0, &operand_data[113], 4, 0, 1, 1 }, { "*msubsf3", "fms.s %0 = %1, %2, %F3%B0", 0, &operand_data[113], 4, 0, 1, 1 }, { "*nmulsf3", "fnmpy.s %0 = %1, %2%B0", 0, &operand_data[113], 3, 0, 1, 1 }, { "*nmaddsf3", "fnma.s %0 = %1, %2, %F3%B0", 0, &operand_data[113], 4, 0, 1, 1 }, { "adddf3", "fadd.d %0 = %1, %F2%B0", (insn_gen_fn) gen_adddf3, &operand_data[117], 3, 0, 1, 1 }, { "subdf3", "fsub.d %0 = %F1, %F2%B0", (insn_gen_fn) gen_subdf3, &operand_data[120], 3, 0, 1, 1 }, { "muldf3", "fmpy.d %0 = %1, %2%B0", (insn_gen_fn) gen_muldf3, &operand_data[123], 3, 0, 1, 1 }, { "absdf2", "fabs %0 = %1%B0", (insn_gen_fn) gen_absdf2, &operand_data[123], 2, 0, 1, 1 }, { "negdf2", "fneg %0 = %1%B0", (insn_gen_fn) gen_negdf2, &operand_data[123], 2, 0, 1, 1 }, { "*nabsdf2", "fnegabs %0 = %1%B0", 0, &operand_data[123], 2, 0, 1, 1 }, { "mindf3", "fmin %0 = %1, %F2%B0", (insn_gen_fn) gen_mindf3, &operand_data[126], 3, 0, 1, 1 }, { "maxdf3", "fmax %0 = %1, %F2%B0", (insn_gen_fn) gen_maxdf3, &operand_data[126], 3, 0, 1, 1 }, { "*madddf3", "fma.d %0 = %1, %2, %F3%B0", 0, &operand_data[129], 4, 0, 1, 1 }, { "*msubdf3", "fms.d %0 = %1, %2, %F3%B0", 0, &operand_data[129], 4, 0, 1, 1 }, { "*nmuldf3", "fnmpy.d %0 = %1, %2%B0", 0, &operand_data[123], 3, 0, 1, 1 }, { "*nmadddf3", "fnma.d %0 = %1, %2, %F3%B0", 0, &operand_data[129], 4, 0, 1, 1 }, { "*ashlsi3_internal", "dep.z %0 = %1, %2, %E2", 0, &operand_data[133], 3, 0, 1, 1 }, { "*ashrsi3_internal", "extr %0 = %1, %2, %E2", 0, &operand_data[136], 3, 0, 1, 1 }, { "*lshrsi3_internal", "extr.u %0 = %1, %2, %E2", 0, &operand_data[136], 3, 0, 1, 1 }, { "ashldi3", "shl %0 = %1, %2", (insn_gen_fn) gen_ashldi3, &operand_data[139], 3, 0, 1, 1 }, { "*shladd", "shladd %0 = %1, %S2, %3", 0, &operand_data[142], 4, 0, 1, 1 }, { "*shladd_elim", "#", 0, &operand_data[146], 5, 0, 1, 1 }, { "ashrdi3", "shr %0 = %1, %2", (insn_gen_fn) gen_ashrdi3, &operand_data[139], 3, 0, 1, 1 }, { "lshrdi3", "shr.u %0 = %1, %2", (insn_gen_fn) gen_lshrdi3, &operand_data[139], 3, 0, 1, 1 }, { "*rotrdi3_internal", "shrp %0 = %1, %1, %2", 0, &operand_data[151], 3, 0, 1, 1 }, { "*one_cmplsi2_internal", "andcm %0 = -1, %1", 0, &operand_data[72], 2, 0, 1, 1 }, { "anddi3", (const PTR) output_86, (insn_gen_fn) gen_anddi3, &operand_data[154], 3, 0, 2, 2 }, { "*andnot", (const PTR) output_87, 0, &operand_data[157], 3, 0, 2, 2 }, { "iordi3", (const PTR) output_88, (insn_gen_fn) gen_iordi3, &operand_data[154], 3, 0, 2, 2 }, { "xordi3", (const PTR) output_89, (insn_gen_fn) gen_xordi3, &operand_data[154], 3, 0, 2, 2 }, { "one_cmpldi2", "andcm %0 = -1, %1", (insn_gen_fn) gen_one_cmpldi2, &operand_data[53], 2, 0, 1, 1 }, { "*cmpsi_normal", "cmp4.%C1 %0, %I0 = %3, %2", 0, &operand_data[160], 4, 0, 1, 1 }, { "*cmpsi_adjusted", "cmp4.%C1 %0, %I0 = %3, %2", 0, &operand_data[164], 4, 0, 1, 1 }, { "*cmpdi_normal", "cmp.%C1 %0, %I0 = %3, %2", 0, &operand_data[168], 4, 0, 1, 1 }, { "*cmpdi_adjusted", "cmp.%C1 %0, %I0 = %3, %2", 0, &operand_data[172], 4, 0, 1, 1 }, { "*cmpsf_internal", "fcmp.%D1 %0, %I0 = %F2, %F3", 0, &operand_data[176], 4, 0, 1, 1 }, { "*cmpdf_internal", "fcmp.%D1 %0, %I0 = %F2, %F3", 0, &operand_data[180], 4, 0, 1, 1 }, { "*bit_zero", "tbit.z %0, %I0 = %1, %2", 0, &operand_data[184], 3, 0, 1, 1 }, { "*bit_one", "tbit.nz %0, %I0 = %1, %2", 0, &operand_data[184], 3, 0, 1, 1 }, { "*movcc_internal", (const PTR) output_99, 0, &operand_data[187], 2, 0, 4, 2 }, { "*br_true", (const PTR) output_100, 0, &operand_data[189], 3, 0, 1, 3 }, { "*br_false", (const PTR) output_101, 0, &operand_data[189], 3, 0, 1, 3 }, { "*sne_internal", "#", 0, &operand_data[192], 2, 0, 1, 1 }, { "*seq_internal", "#", 0, &operand_data[192], 2, 0, 1, 1 }, { "*cmovdi_internal", "#", 0, &operand_data[194], 5, 0, 7, 1 }, { "*absdi2_internal", "#", 0, &operand_data[199], 5, 0, 2, 1 }, { "*cmovsi_internal", "#", 0, &operand_data[204], 5, 0, 7, 1 }, { "*abssi2_internal", "#", 0, &operand_data[209], 5, 0, 2, 1 }, { "call_internal", (const PTR) output_108, (insn_gen_fn) gen_call_internal, &operand_data[214], 3, 0, 1, 3 }, { "*call_internal1", (const PTR) output_109, 0, &operand_data[214], 3, 0, 1, 3 }, { "call_value_internal", (const PTR) output_110, (insn_gen_fn) gen_call_value_internal, &operand_data[217], 4, 0, 1, 3 }, { "*call_value_internal1", (const PTR) output_111, 0, &operand_data[217], 4, 0, 1, 3 }, { "*call_multiple_values_internal1", (const PTR) output_112, 0, &operand_data[221], 5, 0, 1, 3 }, { "return_internal", "br.ret.sptk.many %0", (insn_gen_fn) gen_return_internal, &operand_data[226], 1, 0, 1, 1 }, { "return", "br.ret.sptk.many rp", (insn_gen_fn) gen_return, &operand_data[0], 0, 0, 0, 1 }, { "*return_true", (const PTR) output_115, 0, &operand_data[189], 2, 0, 1, 3 }, { "*return_false", (const PTR) output_116, 0, &operand_data[189], 2, 0, 1, 3 }, { "jump", "br %l0", (insn_gen_fn) gen_jump, &operand_data[191], 1, 0, 0, 1 }, { "indirect_jump", "br %0", (insn_gen_fn) gen_indirect_jump, &operand_data[226], 1, 0, 1, 1 }, { "tablejump_internal", "br %0", (insn_gen_fn) gen_tablejump_internal, &operand_data[226], 2, 0, 1, 1 }, { "prologue_allocate_stack", (const PTR) output_120, (insn_gen_fn) gen_prologue_allocate_stack, &operand_data[228], 4, 1, 3, 2 }, { "epilogue_deallocate_stack", "mov %0 = %1", (insn_gen_fn) gen_epilogue_deallocate_stack, &operand_data[63], 2, 2, 1, 1 }, { "alloc", "alloc %0 = ar.pfs, %1, %2, %3, %4", (insn_gen_fn) gen_alloc, &operand_data[232], 5, 0, 1, 1 }, { "gr_spill", "st8.spill %0 = %1%P0", (insn_gen_fn) gen_gr_spill, &operand_data[237], 2, 0, 1, 1 }, { "gr_restore", "ld8.fill %0 = %1%P1", (insn_gen_fn) gen_gr_restore, &operand_data[239], 2, 0, 1, 1 }, { "fr_spill", "stf.spill %0 = %1%P0", (insn_gen_fn) gen_fr_spill, &operand_data[241], 2, 0, 1, 1 }, { "fr_restore", "ldf.fill %0 = %1%P1", (insn_gen_fn) gen_fr_restore, &operand_data[243], 2, 0, 1, 1 }, { "pr_spill", "mov %0 = pr", (insn_gen_fn) gen_pr_spill, &operand_data[9], 1, 0, 1, 1 }, { "pr_restore", "mov pr = %0, -1", (insn_gen_fn) gen_pr_restore, &operand_data[54], 1, 0, 1, 1 }, { "pfs_restore", "mov ar.pfs = %0", (insn_gen_fn) gen_pfs_restore, &operand_data[54], 1, 0, 1, 1 }, { "unat_spill", "mov %0 = ar.unat", (insn_gen_fn) gen_unat_spill, &operand_data[9], 1, 0, 1, 1 }, { "unat_restore", "mov ar.unat = %0", (insn_gen_fn) gen_unat_restore, &operand_data[54], 1, 0, 1, 1 }, { "bsp_value", "mov %0 = ar.bsp", (insn_gen_fn) gen_bsp_value, &operand_data[9], 1, 0, 1, 1 }, { //wei: compaq c does not like newlines in string literals "set_bsp", "flushrs\n\t" "mov r19=ar.rsc\n\t" ";;\n\t" "and r19=0x1c,r19\n\t" ";;\n\t" "mov ar.rsc=r19\n\t" ";;\n\t" "mov ar.bspstore=%0\n\t" ";;\n\t" "or r19=0x3,r19\n\t" ";;\n\t" "loadrs\n\t" "invala\n\t" ";;\n\t" "mov ar.rsc=r19\n\t", (insn_gen_fn) gen_set_bsp, &operand_data[54], 1, 0, 1, 1 }, { "flushrs", ";; \n\t flushrs", (insn_gen_fn) gen_flushrs, &operand_data[0], 0, 0, 0, 1 }, { "nop", "nop 0", (insn_gen_fn) gen_nop, &operand_data[0], 0, 0, 0, 1 }, { "blockage", "", (insn_gen_fn) gen_blockage, &operand_data[0], 0, 0, 0, 1 }, { "insn_group_barrier", ";;", (insn_gen_fn) gen_insn_group_barrier, &operand_data[0], 0, 0, 0, 1 }, { "flush_cache", "fc %0\n\t;;\n\tadds %0=31,%0\n\t;;\n\tfc %0\n\t;;\n\tsync.i\n\tsrlz.i", (insn_gen_fn) gen_flush_cache, &operand_data[95], 1, 0, 1, 1 }, { "ccv_restore_si", "mov ar.ccv = %0", (insn_gen_fn) gen_ccv_restore_si, &operand_data[67], 1, 0, 1, 1 }, { "ccv_restore_di", "mov ar.ccv = %0", (insn_gen_fn) gen_ccv_restore_di, &operand_data[54], 1, 0, 1, 1 }, { "mf", "mf", (insn_gen_fn) gen_mf, &operand_data[245], 1, 0, 1, 1 }, { "fetchadd_acq_si", "fetchadd4.acq %0 = %1, %2", (insn_gen_fn) gen_fetchadd_acq_si, &operand_data[246], 3, 0, 1, 1 }, { "fetchadd_acq_di", "fetchadd8.acq %0 = %1, %2", (insn_gen_fn) gen_fetchadd_acq_di, &operand_data[249], 3, 0, 1, 1 }, { "cmpxchg_acq_si", "cmpxchg4.acq %0 = %1, %2, ar.ccv", (insn_gen_fn) gen_cmpxchg_acq_si, &operand_data[252], 3, 0, 1, 1 }, { "cmpxchg_acq_di", "cmpxchg8.acq %0 = %1, %2, ar.ccv", (insn_gen_fn) gen_cmpxchg_acq_di, &operand_data[255], 3, 0, 1, 1 }, { "xchgsi", "xchg4 %0 = %1, %2", (insn_gen_fn) gen_xchgsi, &operand_data[258], 3, 1, 1, 1 }, { "xchgdi", "xchg8 %0 = %1, %2", (insn_gen_fn) gen_xchgdi, &operand_data[261], 3, 1, 1, 1 }, { "movqi", 0, (insn_gen_fn) gen_movqi, &operand_data[264], 2, 0, 0, 0 }, { "movhi", 0, (insn_gen_fn) gen_movhi, &operand_data[266], 2, 0, 0, 0 }, { "movsi", 0, (insn_gen_fn) gen_movsi, &operand_data[268], 2, 0, 0, 0 }, { "movdi", 0, (insn_gen_fn) gen_movdi, &operand_data[270], 2, 0, 0, 0 }, { "load_fptr", 0, (insn_gen_fn) gen_load_fptr, &operand_data[272], 2, 2, 0, 0 }, { "load_gprel64", 0, (insn_gen_fn) gen_load_gprel64, &operand_data[274], 2, 2, 0, 0 }, { "load_symptr", 0, (insn_gen_fn) gen_load_symptr, &operand_data[274], 2, 2, 0, 0 }, { "movsf", 0, (insn_gen_fn) gen_movsf, &operand_data[276], 2, 0, 0, 0 }, { "movdf", 0, (insn_gen_fn) gen_movdf, &operand_data[278], 2, 0, 0, 0 }, { "movxf", 0, (insn_gen_fn) gen_movxf, &operand_data[280], 2, 0, 0, 0 }, { "movxf+1", 0, 0, &operand_data[282], 2, 0, 0, 0 }, { "insv", 0, (insn_gen_fn) gen_insv, &operand_data[284], 4, 0, 0, 0 }, { "insv+1", 0, 0, &operand_data[288], 3, 0, 0, 0 }, { "addsi3-1", 0, 0, &operand_data[288], 3, 0, 0, 0 }, { "addsi3", 0, (insn_gen_fn) gen_addsi3, &operand_data[291], 3, 0, 0, 0 }, { "subsi3", 0, (insn_gen_fn) gen_subsi3, &operand_data[294], 3, 0, 0, 0 }, { "mulsi3", 0, (insn_gen_fn) gen_mulsi3, &operand_data[296], 3, 0, 0, 0 }, { "negsi2", 0, (insn_gen_fn) gen_negsi2, &operand_data[291], 2, 0, 0, 0 }, { "abssi2", 0, (insn_gen_fn) gen_abssi2, &operand_data[291], 2, 4, 0, 0 }, { "sminsi3", 0, (insn_gen_fn) gen_sminsi3, &operand_data[296], 3, 4, 0, 0 }, { "smaxsi3", 0, (insn_gen_fn) gen_smaxsi3, &operand_data[296], 3, 4, 0, 0 }, { "uminsi3", 0, (insn_gen_fn) gen_uminsi3, &operand_data[296], 3, 4, 0, 0 }, { "umaxsi3", 0, (insn_gen_fn) gen_umaxsi3, &operand_data[296], 3, 4, 0, 0 }, { "umaxsi3+1", 0, 0, &operand_data[299], 6, 0, 0, 0 }, { "absdi2", 0, (insn_gen_fn) gen_absdi2, &operand_data[288], 2, 4, 0, 0 }, { "smindi3", 0, (insn_gen_fn) gen_smindi3, &operand_data[288], 3, 4, 0, 0 }, { "smaxdi3", 0, (insn_gen_fn) gen_smaxdi3, &operand_data[288], 3, 4, 0, 0 }, { "umindi3", 0, (insn_gen_fn) gen_umindi3, &operand_data[288], 3, 4, 0, 0 }, { "umaxdi3", 0, (insn_gen_fn) gen_umaxdi3, &operand_data[288], 3, 4, 0, 0 }, { "ffsdi2", 0, (insn_gen_fn) gen_ffsdi2, &operand_data[288], 2, 12, 0, 0 }, { "ashlsi3", 0, (insn_gen_fn) gen_ashlsi3, &operand_data[305], 3, 0, 0, 0 }, { "ashrsi3", 0, (insn_gen_fn) gen_ashrsi3, &operand_data[308], 3, 2, 0, 0 }, { "lshrsi3", 0, (insn_gen_fn) gen_lshrsi3, &operand_data[308], 3, 2, 0, 0 }, { "rotrsi3", 0, (insn_gen_fn) gen_rotrsi3, &operand_data[308], 3, 5, 0, 0 }, { "rotrsi3+1", 0, 0, &operand_data[311], 5, 0, 0, 0 }, { "rotrdi3", 0, (insn_gen_fn) gen_rotrdi3, &operand_data[316], 3, 0, 0, 0 }, { "one_cmplsi2", 0, (insn_gen_fn) gen_one_cmplsi2, &operand_data[291], 2, 0, 0, 0 }, { "cmpsi", 0, (insn_gen_fn) gen_cmpsi, &operand_data[319], 2, 0, 0, 0 }, { "cmpdi", 0, (insn_gen_fn) gen_cmpdi, &operand_data[321], 2, 0, 0, 0 }, { "cmpsf", 0, (insn_gen_fn) gen_cmpsf, &operand_data[323], 2, 0, 0, 0 }, { "cmpdf", 0, (insn_gen_fn) gen_cmpdf, &operand_data[325], 2, 0, 0, 0 }, { "cmpxf", 0, (insn_gen_fn) gen_cmpxf, &operand_data[327], 2, 0, 0, 0 }, { "movcc", 0, (insn_gen_fn) gen_movcc, &operand_data[329], 2, 0, 0, 0 }, { "movcc+1", 0, 0, &operand_data[331], 2, 0, 0, 0 }, { "beq", 0, (insn_gen_fn) gen_beq, &operand_data[191], 1, 4, 0, 0 }, { "bne", 0, (insn_gen_fn) gen_bne, &operand_data[191], 1, 4, 0, 0 }, { "blt", 0, (insn_gen_fn) gen_blt, &operand_data[191], 1, 4, 0, 0 }, { "ble", 0, (insn_gen_fn) gen_ble, &operand_data[191], 1, 4, 0, 0 }, { "bgt", 0, (insn_gen_fn) gen_bgt, &operand_data[191], 1, 4, 0, 0 }, { "bge", 0, (insn_gen_fn) gen_bge, &operand_data[191], 1, 4, 0, 0 }, { "bltu", 0, (insn_gen_fn) gen_bltu, &operand_data[191], 1, 4, 0, 0 }, { "bleu", 0, (insn_gen_fn) gen_bleu, &operand_data[191], 1, 4, 0, 0 }, { "bgtu", 0, (insn_gen_fn) gen_bgtu, &operand_data[191], 1, 4, 0, 0 }, { "bgeu", 0, (insn_gen_fn) gen_bgeu, &operand_data[191], 1, 4, 0, 0 }, { "seq", 0, (insn_gen_fn) gen_seq, &operand_data[272], 1, 4, 0, 0 }, { "sne", 0, (insn_gen_fn) gen_sne, &operand_data[272], 1, 4, 0, 0 }, { "slt", 0, (insn_gen_fn) gen_slt, &operand_data[272], 1, 4, 0, 0 }, { "sle", 0, (insn_gen_fn) gen_sle, &operand_data[272], 1, 4, 0, 0 }, { "sgt", 0, (insn_gen_fn) gen_sgt, &operand_data[272], 1, 4, 0, 0 }, { "sge", 0, (insn_gen_fn) gen_sge, &operand_data[272], 1, 4, 0, 0 }, { "sltu", 0, (insn_gen_fn) gen_sltu, &operand_data[272], 1, 4, 0, 0 }, { "sleu", 0, (insn_gen_fn) gen_sleu, &operand_data[272], 1, 4, 0, 0 }, { "sgtu", 0, (insn_gen_fn) gen_sgtu, &operand_data[272], 1, 4, 0, 0 }, { "sgeu", 0, (insn_gen_fn) gen_sgeu, &operand_data[272], 1, 4, 0, 0 }, { "sgeu+1", 0, 0, &operand_data[333], 2, 0, 0, 0 }, { "sgeu+2", 0, 0, &operand_data[333], 2, 0, 0, 0 }, { "sgeu+3", 0, 0, &operand_data[333], 5, 0, 0, 0 }, { "sgeu+4", 0, 0, &operand_data[333], 5, 0, 0, 0 }, { "sgeu+5", 0, 0, &operand_data[338], 5, 0, 0, 0 }, { "call-5", 0, 0, &operand_data[338], 5, 0, 0, 0 }, { "call-4", 0, 0, &operand_data[343], 5, 0, 0, 0 }, { "call-3", 0, 0, &operand_data[343], 5, 0, 0, 0 }, { "call-2", 0, 0, &operand_data[348], 5, 0, 0, 0 }, { "call-1", 0, 0, &operand_data[348], 5, 0, 0, 0 }, { "call", 0, (insn_gen_fn) gen_call, &operand_data[353], 4, 0, 0, 0 }, { "indirect_call_pic", 0, (insn_gen_fn) gen_indirect_call_pic, &operand_data[354], 2, 7, 0, 0 }, { "setjmp_call_pic", 0, (insn_gen_fn) gen_setjmp_call_pic, &operand_data[354], 2, 2, 0, 0 }, { "call_pic", 0, (insn_gen_fn) gen_call_pic, &operand_data[354], 2, 2, 0, 0 }, { "call_value", 0, (insn_gen_fn) gen_call_value, &operand_data[356], 5, 0, 0, 0 }, { "indirect_call_value_pic", 0, (insn_gen_fn) gen_indirect_call_value_pic, &operand_data[354], 3, 7, 0, 0 }, { "indirect_call_multiple_values_pic", 0, (insn_gen_fn) gen_indirect_call_multiple_values_pic, &operand_data[361], 2, 7, 0, 0 }, { "setjmp_call_value_pic", 0, (insn_gen_fn) gen_setjmp_call_value_pic, &operand_data[354], 3, 2, 0, 0 }, { "call_value_pic", 0, (insn_gen_fn) gen_call_value_pic, &operand_data[354], 3, 2, 0, 0 }, { "call_multiple_values_pic", 0, (insn_gen_fn) gen_call_multiple_values_pic, &operand_data[0], 0, 3, 0, 0 }, { "untyped_call", 0, (insn_gen_fn) gen_untyped_call, &operand_data[354], 3, 0, 0, 0 }, { "tablejump", 0, (insn_gen_fn) gen_tablejump, &operand_data[363], 2, 0, 0, 0 }, { "prologue", 0, (insn_gen_fn) gen_prologue, &operand_data[0], 0, 0, 0, 0 }, { "epilogue", 0, (insn_gen_fn) gen_epilogue, &operand_data[0], 0, 0, 0, 0 }, { "save_stack_nonlocal", 0, (insn_gen_fn) gen_save_stack_nonlocal, &operand_data[365], 2, 0, 0, 0 }, { "nonlocal_goto", 0, (insn_gen_fn) gen_nonlocal_goto, &operand_data[367], 4, 0, 0, 0 }, { "nonlocal_goto_receiver", 0, (insn_gen_fn) gen_nonlocal_goto_receiver, &operand_data[0], 0, 0, 0, 0 }, { "eh_epilogue", 0, (insn_gen_fn) gen_eh_epilogue, &operand_data[371], 3, 0, 1, 0 }, { "restore_stack_nonlocal", 0, (insn_gen_fn) gen_restore_stack_nonlocal, &operand_data[374], 2, 0, 0, 0 }, { "val_compare_and_swap_si", 0, (insn_gen_fn) gen_val_compare_and_swap_si, &operand_data[376], 4, 0, 1, 0 }, { "val_compare_and_swap_di", 0, (insn_gen_fn) gen_val_compare_and_swap_di, &operand_data[380], 4, 0, 1, 0 }, { "lock_test_and_set_si", 0, (insn_gen_fn) gen_lock_test_and_set_si, &operand_data[384], 3, 0, 1, 0 }, { "lock_test_and_set_di", 0, (insn_gen_fn) gen_lock_test_and_set_di, &operand_data[387], 3, 0, 1, 0 }, { "fetch_and_add_si", 0, (insn_gen_fn) gen_fetch_and_add_si, &operand_data[390], 3, 0, 1, 0 }, { "fetch_and_sub_si", 0, (insn_gen_fn) gen_fetch_and_sub_si, &operand_data[384], 3, 0, 1, 0 }, { "fetch_and_or_si", 0, (insn_gen_fn) gen_fetch_and_or_si, &operand_data[384], 3, 0, 1, 0 }, { "fetch_and_and_si", 0, (insn_gen_fn) gen_fetch_and_and_si, &operand_data[384], 3, 0, 1, 0 }, { "fetch_and_xor_si", 0, (insn_gen_fn) gen_fetch_and_xor_si, &operand_data[384], 3, 0, 1, 0 }, { "fetch_and_nand_si", 0, (insn_gen_fn) gen_fetch_and_nand_si, &operand_data[384], 3, 0, 1, 0 }, { "fetch_and_add_di", 0, (insn_gen_fn) gen_fetch_and_add_di, &operand_data[393], 3, 0, 1, 0 }, { "fetch_and_sub_di", 0, (insn_gen_fn) gen_fetch_and_sub_di, &operand_data[387], 3, 0, 1, 0 }, { "fetch_and_or_di", 0, (insn_gen_fn) gen_fetch_and_or_di, &operand_data[387], 3, 0, 1, 0 }, { "fetch_and_and_di", 0, (insn_gen_fn) gen_fetch_and_and_di, &operand_data[387], 3, 0, 1, 0 }, { "fetch_and_xor_di", 0, (insn_gen_fn) gen_fetch_and_xor_di, &operand_data[387], 3, 0, 1, 0 }, { "fetch_and_nand_di", 0, (insn_gen_fn) gen_fetch_and_nand_di, &operand_data[387], 3, 0, 1, 0 }, { "add_and_fetch_di", 0, (insn_gen_fn) gen_add_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "sub_and_fetch_di", 0, (insn_gen_fn) gen_sub_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "or_and_fetch_di", 0, (insn_gen_fn) gen_or_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "and_and_fetch_di", 0, (insn_gen_fn) gen_and_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "xor_and_fetch_di", 0, (insn_gen_fn) gen_xor_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "nand_and_fetch_di", 0, (insn_gen_fn) gen_nand_and_fetch_di, &operand_data[387], 3, 0, 1, 0 }, { "add_and_fetch_si", 0, (insn_gen_fn) gen_add_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "sub_and_fetch_si", 0, (insn_gen_fn) gen_sub_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "or_and_fetch_si", 0, (insn_gen_fn) gen_or_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "and_and_fetch_si", 0, (insn_gen_fn) gen_and_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "xor_and_fetch_si", 0, (insn_gen_fn) gen_xor_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "nand_and_fetch_si", 0, (insn_gen_fn) gen_nand_and_fetch_si, &operand_data[384], 3, 0, 1, 0 }, { "nand_and_fetch_si+1", (const PTR) output_269, 0, &operand_data[396], 4, 0, 6, 2 }, { "nand_and_fetch_si+2", (const PTR) output_270, 0, &operand_data[400], 4, 0, 6, 2 }, { "nand_and_fetch_si+3", (const PTR) output_271, 0, &operand_data[404], 4, 0, 10, 2 }, { "nand_and_fetch_si+4", (const PTR) output_272, 0, &operand_data[408], 4, 0, 12, 2 }, { "nand_and_fetch_si+5", "(%J2) addl %0 = @ltoff(@fptr(%1)), gp", 0, &operand_data[412], 4, 0, 1, 1 }, { "nand_and_fetch_si+6", "(%J2) addl %0 = @gprel(%1), gp", 0, &operand_data[416], 4, 0, 1, 1 }, { "nand_and_fetch_si+7", "(%J2) movl %0 = @gprel(%1)", 0, &operand_data[420], 4, 0, 1, 1 }, { "nand_and_fetch_si+8", "(%J2) addl %0 = @ltoff(%1), gp", 0, &operand_data[424], 4, 0, 1, 1 }, { "nand_and_fetch_si+9", (const PTR) output_277, 0, &operand_data[428], 4, 0, 7, 2 }, { "nand_and_fetch_si+10", (const PTR) output_278, 0, &operand_data[432], 4, 0, 6, 2 }, { "nand_and_fetch_si+11", (const PTR) output_279, 0, &operand_data[436], 4, 0, 3, 2 }, { "nand_and_fetch_si+12", "(%J2) sxt1 %0 = %1", 0, &operand_data[440], 4, 0, 1, 1 }, { "nand_and_fetch_si+13", "(%J2) sxt2 %0 = %1", 0, &operand_data[444], 4, 0, 1, 1 }, { "nand_and_fetch_si+14", (const PTR) output_282, 0, &operand_data[448], 4, 0, 2, 2 }, { "nand_and_fetch_si+15", (const PTR) output_283, 0, &operand_data[452], 4, 0, 2, 2 }, { "nand_and_fetch_si+16", (const PTR) output_284, 0, &operand_data[456], 4, 0, 2, 2 }, { "nand_and_fetch_si+17", (const PTR) output_285, 0, &operand_data[460], 4, 0, 3, 2 }, { "nand_and_fetch_si+18", "(%J2) mov %0 = %1", 0, &operand_data[464], 4, 0, 2, 1 }, { "nand_and_fetch_si+19", "(%J2) fnorm.s %0 = %1%B0", 0, &operand_data[468], 4, 0, 1, 1 }, { "nand_and_fetch_si+20", "(%J2) fnorm.s %0 = %1%B0", 0, &operand_data[472], 4, 0, 1, 1 }, { "nand_and_fetch_si+21", "(%J2) fnorm.d %0 = %1%B0", 0, &operand_data[476], 4, 0, 1, 1 }, { "nand_and_fetch_si+22", "(%J2) fcvt.xf %0 = %1", 0, &operand_data[480], 4, 0, 1, 1 }, { "nand_and_fetch_si+23", "(%J2) fcvt.fx.trunc %0 = %1%B0", 0, &operand_data[484], 4, 0, 1, 1 }, { "nand_and_fetch_si+24", "(%J2) fcvt.fx.trunc %0 = %1%B0", 0, &operand_data[488], 4, 0, 1, 1 }, { "nand_and_fetch_si+25", "(%J2) fcvt.xuf.s %0 = %1%B0", 0, &operand_data[492], 4, 0, 1, 1 }, { "nand_and_fetch_si+26", "(%J2) fcvt.xuf.d %0 = %1%B0", 0, &operand_data[496], 4, 0, 1, 1 }, { "nand_and_fetch_si+27", "(%J2) fcvt.fxu.trunc %0 = %1%B0", 0, &operand_data[484], 4, 0, 1, 1 }, { "nand_and_fetch_si+28", "(%J2) fcvt.fxu.trunc %0 = %1%B0", 0, &operand_data[488], 4, 0, 1, 1 }, { "nand_and_fetch_si+29", "(%J4) extr %0 = %1, %3, %2", 0, &operand_data[500], 6, 0, 1, 1 }, { "nand_and_fetch_si+30", "(%J4) extr.u %0 = %1, %3, %2", 0, &operand_data[500], 6, 0, 1, 1 }, { "nand_and_fetch_si+31", "(%J4) dep %0 = %3, %0, %2, %1", 0, &operand_data[506], 6, 0, 1, 1 }, { "nand_and_fetch_si+32", "(%J3) #", 0, &operand_data[512], 5, 0, 1, 1 }, { "nand_and_fetch_si+33", "(%J2) mix4.l %0 = %0, %r1", 0, &operand_data[517], 4, 0, 1, 1 }, { "nand_and_fetch_si+34", "(%J2) mix4.r %0 = %r1, %0", 0, &operand_data[521], 4, 0, 1, 1 }, { "nand_and_fetch_si+35", "(%J3) mix4.r %0 = %2, %1", 0, &operand_data[525], 5, 0, 1, 1 }, { "nand_and_fetch_si+36", (const PTR) output_304, 0, &operand_data[530], 5, 0, 3, 2 }, { "nand_and_fetch_si+37", "(%J3) add %0 = %1, %2, 1", 0, &operand_data[535], 5, 0, 1, 1 }, { "nand_and_fetch_si+38", "(%J3) sub %0 = %1, %2", 0, &operand_data[540], 5, 0, 1, 1 }, { "nand_and_fetch_si+39", "(%J3) sub %0 = %2, %1, 1", 0, &operand_data[535], 5, 0, 1, 1 }, { "nand_and_fetch_si+40", "(%J3) xma.l %0 = %1, %2, f0%B0", 0, &operand_data[545], 5, 0, 1, 1 }, { "nand_and_fetch_si+41", "(%J2) sub %0 = r0, %1", 0, &operand_data[550], 4, 0, 1, 1 }, { "nand_and_fetch_si+42", (const PTR) output_310, 0, &operand_data[554], 5, 0, 3, 2 }, { "nand_and_fetch_si+43", "(%J3) add %0 = %1, %2, 1", 0, &operand_data[559], 5, 0, 1, 1 }, { "nand_and_fetch_si+44", "(%J3) sub %0 = %1, %2", 0, &operand_data[564], 5, 0, 1, 1 }, { "nand_and_fetch_si+45", "(%J3) sub %0 = %2, %1, 1", 0, &operand_data[559], 5, 0, 1, 1 }, { "nand_and_fetch_si+46", "(%J3) xma.l %0 = %1, %2, f0%B0", 0, &operand_data[569], 5, 0, 1, 1 }, { "nand_and_fetch_si+47", "(%J5) xma.l %0 = %1, %2, %3%B0", 0, &operand_data[574], 7, 0, 1, 1 }, { "nand_and_fetch_si+48", "(%J6) #", 0, &operand_data[581], 8, 0, 1, 1 }, { "nand_and_fetch_si+49", "(%J3) xma.h %0 = %1, %2, f0%B0", 0, &operand_data[569], 5, 0, 1, 1 }, { "nand_and_fetch_si+50", "(%J3) xma.hu %0 = %1, %2, f0%B0", 0, &operand_data[569], 5, 0, 1, 1 }, { "nand_and_fetch_si+51", "(%J2) sub %0 = r0, %1", 0, &operand_data[589], 4, 0, 1, 1 }, { "nand_and_fetch_si+52", "(%J2) popcnt %0 = %1", 0, &operand_data[589], 4, 0, 1, 1 }, { "nand_and_fetch_si+53", "(%J3) fadd.s %0 = %1, %F2%B0", 0, &operand_data[593], 5, 0, 1, 1 }, { "nand_and_fetch_si+54", "(%J3) fsub.s %0 = %F1, %F2%B0", 0, &operand_data[598], 5, 0, 1, 1 }, { "nand_and_fetch_si+55", "(%J3) fmpy.s %0 = %1, %2%B0", 0, &operand_data[603], 5, 0, 1, 1 }, { "nand_and_fetch_si+56", "(%J2) fabs %0 = %1%B0", 0, &operand_data[608], 4, 0, 1, 1 }, { "nand_and_fetch_si+57", "(%J2) fneg %0 = %1%B0", 0, &operand_data[608], 4, 0, 1, 1 }, { "nand_and_fetch_si+58", "(%J2) fnegabs %0 = %1%B0", 0, &operand_data[608], 4, 0, 1, 1 }, { "nand_and_fetch_si+59", "(%J3) fmin %0 = %1, %F2%B0", 0, &operand_data[612], 5, 0, 1, 1 }, { "nand_and_fetch_si+60", "(%J3) fmax %0 = %1, %F2%B0", 0, &operand_data[612], 5, 0, 1, 1 }, { "nand_and_fetch_si+61", "(%J4) fma.s %0 = %1, %2, %F3%B0", 0, &operand_data[617], 6, 0, 1, 1 }, { "nand_and_fetch_si+62", "(%J4) fms.s %0 = %1, %2, %F3%B0", 0, &operand_data[617], 6, 0, 1, 1 }, { "nand_and_fetch_si+63", "(%J3) fnmpy.s %0 = %1, %2%B0", 0, &operand_data[623], 5, 0, 1, 1 }, { "nand_and_fetch_si+64", "(%J4) fnma.s %0 = %1, %2, %F3%B0", 0, &operand_data[617], 6, 0, 1, 1 }, { "nand_and_fetch_si+65", "(%J3) fadd.d %0 = %1, %F2%B0", 0, &operand_data[628], 5, 0, 1, 1 }, { "nand_and_fetch_si+66", "(%J3) fsub.d %0 = %F1, %F2%B0", 0, &operand_data[633], 5, 0, 1, 1 }, { "nand_and_fetch_si+67", "(%J3) fmpy.d %0 = %1, %2%B0", 0, &operand_data[638], 5, 0, 1, 1 }, { "nand_and_fetch_si+68", "(%J2) fabs %0 = %1%B0", 0, &operand_data[643], 4, 0, 1, 1 }, { "nand_and_fetch_si+69", "(%J2) fneg %0 = %1%B0", 0, &operand_data[643], 4, 0, 1, 1 }, { "nand_and_fetch_si+70", "(%J2) fnegabs %0 = %1%B0", 0, &operand_data[643], 4, 0, 1, 1 }, { "nand_and_fetch_si+71", "(%J3) fmin %0 = %1, %F2%B0", 0, &operand_data[647], 5, 0, 1, 1 }, { "nand_and_fetch_si+72", "(%J3) fmax %0 = %1, %F2%B0", 0, &operand_data[647], 5, 0, 1, 1 }, { "nand_and_fetch_si+73", "(%J4) fma.d %0 = %1, %2, %F3%B0", 0, &operand_data[652], 6, 0, 1, 1 }, { "nand_and_fetch_si+74", "(%J4) fms.d %0 = %1, %2, %F3%B0", 0, &operand_data[652], 6, 0, 1, 1 }, { "nand_and_fetch_si+75", "(%J3) fnmpy.d %0 = %1, %2%B0", 0, &operand_data[638], 5, 0, 1, 1 }, { "nand_and_fetch_si+76", "(%J4) fnma.d %0 = %1, %2, %F3%B0", 0, &operand_data[652], 6, 0, 1, 1 }, { "nand_and_fetch_si+77", "(%J3) dep.z %0 = %1, %2, %E2", 0, &operand_data[658], 5, 0, 1, 1 }, { "nand_and_fetch_si+78", "(%J3) extr %0 = %1, %2, %E2", 0, &operand_data[663], 5, 0, 1, 1 }, { "nand_and_fetch_si+79", "(%J3) extr.u %0 = %1, %2, %E2", 0, &operand_data[663], 5, 0, 1, 1 }, { "nand_and_fetch_si+80", "(%J3) shl %0 = %1, %2", 0, &operand_data[668], 5, 0, 1, 1 }, { "nand_and_fetch_si+81", "(%J4) shladd %0 = %1, %S2, %3", 0, &operand_data[673], 6, 0, 1, 1 }, { "nand_and_fetch_si+82", "(%J5) #", 0, &operand_data[679], 7, 0, 1, 1 }, { "nand_and_fetch_si+83", "(%J3) shr %0 = %1, %2", 0, &operand_data[668], 5, 0, 1, 1 }, { "nand_and_fetch_si+84", "(%J3) shr.u %0 = %1, %2", 0, &operand_data[668], 5, 0, 1, 1 }, { "nand_and_fetch_si+85", "(%J3) shrp %0 = %1, %1, %2", 0, &operand_data[686], 5, 0, 1, 1 }, { "nand_and_fetch_si+86", "(%J2) andcm %0 = -1, %1", 0, &operand_data[550], 4, 0, 1, 1 }, { "nand_and_fetch_si+87", (const PTR) output_355, 0, &operand_data[691], 5, 0, 2, 2 }, { "nand_and_fetch_si+88", (const PTR) output_356, 0, &operand_data[696], 5, 0, 2, 2 }, { "nand_and_fetch_si+89", (const PTR) output_357, 0, &operand_data[691], 5, 0, 2, 2 }, { "nand_and_fetch_si+90", (const PTR) output_358, 0, &operand_data[691], 5, 0, 2, 2 }, { "nand_and_fetch_si+91", "(%J2) andcm %0 = -1, %1", 0, &operand_data[589], 4, 0, 1, 1 }, { "nand_and_fetch_si+92", "(%J4) cmp4.%C1 %0, %I0 = %3, %2", 0, &operand_data[701], 6, 0, 1, 1 }, { "nand_and_fetch_si+93", "(%J4) cmp4.%C1 %0, %I0 = %3, %2", 0, &operand_data[707], 6, 0, 1, 1 }, { "nand_and_fetch_si+94", "(%J4) cmp.%C1 %0, %I0 = %3, %2", 0, &operand_data[713], 6, 0, 1, 1 }, { "nand_and_fetch_si+95", "(%J4) cmp.%C1 %0, %I0 = %3, %2", 0, &operand_data[719], 6, 0, 1, 1 }, { "nand_and_fetch_si+96", "(%J4) fcmp.%D1 %0, %I0 = %F2, %F3", 0, &operand_data[725], 6, 0, 1, 1 }, { "nand_and_fetch_si+97", "(%J4) fcmp.%D1 %0, %I0 = %F2, %F3", 0, &operand_data[731], 6, 0, 1, 1 }, { "nand_and_fetch_si+98", "(%J3) tbit.z %0, %I0 = %1, %2", 0, &operand_data[737], 5, 0, 1, 1 }, { "nand_and_fetch_si+99", "(%J3) tbit.nz %0, %I0 = %1, %2", 0, &operand_data[737], 5, 0, 1, 1 }, { "nand_and_fetch_si+100", (const PTR) output_368, 0, &operand_data[742], 4, 0, 4, 2 }, { "nand_and_fetch_si+101", "(%J2) #", 0, &operand_data[746], 4, 0, 1, 1 }, { "nand_and_fetch_si+102", "(%J2) #", 0, &operand_data[746], 4, 0, 1, 1 }, { "nand_and_fetch_si+103", "(%J5) #", 0, &operand_data[750], 7, 0, 7, 1 }, { "nand_and_fetch_si+104", "(%J5) #", 0, &operand_data[757], 7, 0, 2, 1 }, { "nand_and_fetch_si+105", "(%J5) #", 0, &operand_data[764], 7, 0, 7, 1 }, { "nand_and_fetch_si+106", "(%J5) #", 0, &operand_data[771], 7, 0, 2, 1 }, { "nand_and_fetch_si+107", (const PTR) output_375, 0, &operand_data[778], 5, 0, 1, 3 }, { "nand_and_fetch_si+108", (const PTR) output_376, 0, &operand_data[778], 5, 0, 1, 3 }, { "nand_and_fetch_si+109", (const PTR) output_377, 0, &operand_data[783], 6, 0, 1, 3 }, { "nand_and_fetch_si+110", (const PTR) output_378, 0, &operand_data[783], 6, 0, 1, 3 }, { "nand_and_fetch_si+111", (const PTR) output_379, 0, &operand_data[789], 7, 0, 1, 3 }, { "nand_and_fetch_si+112", "(%J1) br.ret.sptk.many %0", 0, &operand_data[796], 3, 0, 1, 1 }, { "nand_and_fetch_si+113", "(%J0) br.ret.sptk.many rp", 0, &operand_data[189], 2, 0, 1, 1 }, { "nand_and_fetch_si+114", "(%J1) br %l0", 0, &operand_data[799], 3, 0, 1, 1 }, { "nand_and_fetch_si+115", "(%J1) br %0", 0, &operand_data[796], 3, 0, 1, 1 }, { "nand_and_fetch_si+116", "(%J2) br %0", 0, &operand_data[802], 4, 0, 1, 1 }, { "nand_and_fetch_si+117", (const PTR) output_385, 0, &operand_data[806], 6, 1, 3, 2 }, { "nand_and_fetch_si+118", "(%J2) mov %0 = %1", 0, &operand_data[812], 4, 2, 1, 1 }, { "nand_and_fetch_si+119", "(%J2) st8.spill %0 = %1%P0", 0, &operand_data[816], 4, 0, 1, 1 }, { "nand_and_fetch_si+120", "(%J2) ld8.fill %0 = %1%P1", 0, &operand_data[820], 4, 0, 1, 1 }, { "nand_and_fetch_si+121", "(%J2) stf.spill %0 = %1%P0", 0, &operand_data[824], 4, 0, 1, 1 }, { "nand_and_fetch_si+122", "(%J2) ldf.fill %0 = %1%P1", 0, &operand_data[828], 4, 0, 1, 1 }, { "nand_and_fetch_si+123", "(%J1) mov %0 = pr", 0, &operand_data[514], 3, 0, 1, 1 }, { "nand_and_fetch_si+124", "(%J1) mov pr = %0, -1", 0, &operand_data[518], 3, 0, 1, 1 }, { "nand_and_fetch_si+125", "(%J1) mov ar.pfs = %0", 0, &operand_data[518], 3, 0, 1, 1 }, { "nand_and_fetch_si+126", "(%J1) mov %0 = ar.unat", 0, &operand_data[514], 3, 0, 1, 1 }, { "nand_and_fetch_si+127", "(%J1) mov ar.unat = %0", 0, &operand_data[518], 3, 0, 1, 1 }, { "nand_and_fetch_si+128", "(%J1) mov %0 = ar.bsp", 0, &operand_data[514], 3, 0, 1, 1 }, { "nand_and_fetch_si+129", "(%J0) ;; \n\t flushrs", 0, &operand_data[189], 2, 0, 1, 1 }, { "nand_and_fetch_si+130", "(%J0) nop 0", 0, &operand_data[189], 2, 0, 1, 1 }, { "nand_and_fetch_si+131", "(%J1) mov ar.ccv = %0", 0, &operand_data[527], 3, 0, 1, 1 }, { "nand_and_fetch_si+132", "(%J1) mov ar.ccv = %0", 0, &operand_data[518], 3, 0, 1, 1 }, { "nand_and_fetch_si+133", "(%J1) mf", 0, &operand_data[832], 3, 0, 1, 1 }, { "nand_and_fetch_si+134", "(%J3) fetchadd4.acq %0 = %1, %2", 0, &operand_data[835], 5, 0, 1, 1 }, { "nand_and_fetch_si+135", "(%J3) fetchadd8.acq %0 = %1, %2", 0, &operand_data[840], 5, 0, 1, 1 }, { "nand_and_fetch_si+136", "(%J3) cmpxchg4.acq %0 = %1, %2, ar.ccv", 0, &operand_data[845], 5, 0, 1, 1 }, { "nand_and_fetch_si+137", "(%J3) cmpxchg8.acq %0 = %1, %2, ar.ccv", 0, &operand_data[850], 5, 0, 1, 1 }, { "nand_and_fetch_si+138", "(%J3) xchg4 %0 = %1, %2", 0, &operand_data[855], 5, 1, 1, 1 }, { "nand_and_fetch_si+139", "(%J3) xchg8 %0 = %1, %2", 0, &operand_data[860], 5, 1, 1, 1 }, }; const char * get_insn_name (code) int code; { return insn_data[code].name; }